1. Field of the Invention
The present invention relates to an improvement in semiconductor full adder.
2. Description of the Prior Art:
The conventional full adder has been constituted as shown in FIG. 1. This circuit receives a first input signal A and a second input signal B which are to be mutually summed and a carry input signal C.sub.i, and outputs summed signal S and a carry output signal C.sub.o. The circuit comprises NOR gates 1 and 2, AND.NOR complex gates 3 and 4 and NAND gates 5, 6 and 7. The above-mentioned gates are all constituted by known CMOS gates. Combination of the NOR gate 1 and the complex gate 3 and another combination of the NOR gate 2 and the complex gate 4 each has a function of exclusive OR gate (EXOR gate). Accordingly, the sum output signal S and carry output signal C.sub.o are represented as follows: ##EQU1##
The above-mentioned conventional full adder circuit has a problem that when the input signals A, B and C.sub.i are simultaneously input to the circuit, then the sum output signal S is obtained after propagation of the input signals through the gates 1, 3, 2 and 4, that is four stages of the logic gates, and accordingly, a process time becomes sum of delay times of the four gates. On the other hand, the output carry signal C.sub.o is issued by passing the input signal through the gates 1, 3, 6 and 7, that is, four stages of gates, accordingly it also requires a process time of a sum of delay times of the four gates. That is, the conventional full adder of FIG. 1 has a long processing time.